happsky
Advanced Member level 4
Code:
module WR_RD_DSP16_clk(clk,
DSP_ECLKOUT,
DSP_ED,
nWR,
nRD,
data
);
input clk;//不同时钟域的clk
input DSP_ECLKOUT;
inout [15:0] DSP_ED;
input nWR;
input nRD;
output [15:0] data;reg [15:0] data;
reg [15:0] dsp_data;
always @(posedge DSP_ECLKOUT)
if(~nWR)
dsp_data[15:0]<=DSP_ED[15:0];
else
dsp_data[15:0]<=dsp_data[15:0];
assign DSP_ED[15:0]=(nRD) ? 16'hzzzz:dsp_data[15:0];
always @(posedge clk)
data[15:0]<=dsp_data[15:0];
endmodulewhere nWR and nRD is:
Code:
nWR =~(~DSP_CE& ~DSP_AWE& (DSP_EA[21:2]==20'h00000));
nRD =~(~DSP_CE& ~DSP_ARE&~DSP_AOE&(DSP_EA[21:2]==20'h00000));Dear all:
This is a code read and write SDRAM,but I don't know it is synchronization or asynchrony,I think SDRAM must be synchronization ,but it's seem be asynchrony from the code.
And what the function of this sentence:
Code:
assign DSP_ED[15:0]=(nRD) ? 16'hzzzz:dsp_data[15:0];Thank you very much!:razz: