synchronization between 2 clock domains

synchronization of 2 clocks

hey!
i m trying to synchronize between 2 clock domains which differ only slighlty in frequency(mesosynchronous). the problem is that the counters used in both domains increment by a value of 2 whenver the data goes from high to low. the counters should actually increment by 1 which they do when there is no data on the data bus and even for the rising edge of the data.
at negative edges of the data the counters misbehave e.g instead of going from 1 to 2 it goes from 1 to 3. i have figured out that the counter block get activated on both the edges of clock when data goes high to low whereas it should only be activated at rising edges..i am using spartan 3 fpga
here are the codes
///simple counter
module counter(clk,count,reset);
input clk,reset;
output [1:0] count;
reg [1:0] count;

always @ (posedge clk or posedge reset)//posedge
if (reset)
count<=2'b00;
else if (count==2'b11)
count<=2'b01;
else
count<=count+1'b1;




// onehot coder
module count_ring(clk,in_count,out_count);
input clk;
input [1:0] in_count;
output [2:0] out_count;
reg [2:0] out_count;
always @ (negedge clk)//posedge
case (in_count)

2'b01: out_count<=3'b001;
2'b10: out_count<=3'b010;
2'b11: out_count<=3'b100;
default : out_count<=3'b000;
endcase



endmodule

2 clk counter

Hi,

Try this one!

yaqub said:

///simple counter
module counter(clk,count,reset);
input clk,reset;
output [1:0] count;
reg [1:0] count;

always @ (posedge clk or posedge reset)//posedge
if (reset)
count<=2'b00;
else if (count==2'b11)
count<=2'b01;
else
count<=count+1'b1;




// onehot coder
module count_ring(clk,in_count,out_count, reset);
input clk;
input reset;
input [1:0] in_count, in_count_f1, in_count_f2;
output [2:0] out_count;
reg [2:0] out_count;

always @ (posedge clk or negedge reset)
begin
if (~ reset)
begin
in_count_f1 <= 2'b0;
in_count_f2 <= 2'b0;
end
else
begin
in_count_f1 <= in_count;
in_count_f2 <= in_count_f1;
end
end

always @ (posedge clk)//posedge
case (in_count_f2 )

2'b01: out_count<=3'b001;
2'b10: out_count<=3'b010;
2'b11: out_count<=3'b100;
default : out_count<=3'b000;
endcase



endmodule

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