Regarding the DFT issue, I think some of the previous posts are misleading. The main goal is make sure that the reset signal does not conflict with our scan operation.
The first thing you need to study is your scan flip-flop library cell to see if scan-enable or reset has higher priority. In general, async reset has the highest priority, so if you use async reset flip-flops, you have to make sure that the reset line connected to this flip-flop is directly controllable from the chip pins during scan.
Flip-flops with synchronous reset may have different flavors. If scan has priority, then there is no issue of reset conflict. However, if reset has priority, then same rules as async reset applies.
The next thing to consider is the whole reset distribution in the chip. If you are using async reset assertion and sync reset deassertion, you must have reset synchronizers in your path, which under scan mode, you must bypass with a scan mode signal.
Same thing with any reset signal staging with flip-flops, synchronous or otherwise. They all need to be bypassed during scan.