Symmetrical Load Ring Oscillator Design

[ccw27]

ring oscillator design

Can anyone offer me tips on how to size the transistors for the buffer stage shown, particularly the PMOS transistors because I am having a hard time keeping PMOS load in triode and PMOS diode in saturation.

I am trying to build a four stage ring oscillator. From my calculations I need at least a Gain of 1.4 in each delay cell and I am targeting an oscillating frequency of 250 MHz.

Any help or links or papers will be appreciated.

Thanks

 

[aicer]

vco psrr

i think u should to know the meanings of symmetric loads,u could search the paper "Low-Jitter Process-Independent DLL and PLL Based on Self-Biased Techniques" by John G. Maneatis...Besides, u should design another circuit(self-biased replica stage) to provide Vctrl and Vbias which the two voltage are dependent.If u do not produce the self-biases stage,the advantages of symmetric loads will be Vanished!!This paper is classical one in the oscillator. I suggest u reading it

 

[ccw27]

four stages ring oscillator

Yea I have implemented the self-biased ckt. I am trying to meet the spec of Δf/ΔVdd<1%. How much variation in Vdd should I design up to? I am using 2.8 V supply voltage in TSMC 0.18 process.

Thanks

 

[jcpu]

symmetric load

HELLO

spec of Δf/ΔVdd<1%

is difficult to translate for me since there are different unit,
when trying to compare this example:

I have on my hand a 4MHz maneatis type PLL,
performance is all right, <100 psec jitter, but
Δf ~ 10% when under ~ 10% Vdd noise,
.... is that reasonable? or something could be done?

Thanks in advance,

 

[yankuangtu]

symmetric load high freq

for this delay cell it's not diffcult to archieve the target,maybe you can add a voltage regulator for VCO to archieve high PSRR

 

[neoflash]

ring-oscillator vco with a three transistor load

the psrr should be very good for this kind of VCO. How you set up your simulation deck for PSRR?

 

[darkk]

symmetric load in vco

If my memory serves me right, this kinda VCO's phase noise performance is OK but not that good, compared to other ringoscl-based VCO. Even in terms of the PSRR, it's not the best actually.

 

[jcpu]

transistor loads in a ring oscillator

neoflash said

the psrr should be very good for this kind of VCO. How you set up your simulation deck for PSRR?

Yes, you are right:
Need help about how to simulate PSRR of PLL under lock,
what I have is silicon data...

 

[neoflash]

symmetric load vco

If my memory serves me right, this kinda VCO's phase noise performance is OK but not that good, compared to other ringoscl-based VCO. Even in terms of the PSRR, it's not the best actually.

can you give some example better?

 

[darkk]

self bias pll design simulation unit delay cell

The symmetric-load-structure provides smaller voltage swing, which to some degree could degrade the phase noise performance.

In terms of PSRR, the level shifter structure can also achieve better performance, esp. in higher BW.

In my opion, the symmetric load PLUS replica bias (refer to Manaetis' paper, but not sure of the spell of the name) does provide the decent performance in average, though the symmetric load and replica bias weren't original concept.

 

[neoflash]

design and simulation of self biased pll design

wow...

I can not agree on this. Just give some better example.

 

[anil.p]

low voltage high psrr ring oscillators

hi ,

is it neccessary that input transistors of dealy cell in symmetric load vco must be in saturation? if it neceessary then how to choose w/l ratios of delay cell.and can anybody send current waveforms of input transistors.

Thanks,
anil

 

[sudheerkm]

maneatus vco design

why u use a differentialstructure u could have used current starved inverters

 

[anil.p]

symmetric load biasing

if you use differential structure then it eliminates common mode noise.

 

[yashiro]

symmetric loads in vco

neoflash said

the psrr should be very good for this kind of VCO. How you set up your simulation deck for PSRR?

Yes, you are right:
Need help about how to simulate PSRR of PLL under lock,
what I have is silicon data...

Just make an ac analysis where you place ac=1 for the power supply voltage source and check the output.

 

[tzg6sa]

replica biasing ring oscillator

About PSRR. In Maneatis' paper there is a very good PSRR value. But be carefull with it. If I remember correctly then this value is meant as DC value. At high frequencies the PSRR will degrade due to the capacitance of the common source node to the ground and due to the finite bandwidth of the bias circuit.
I have simulated this structure too, but I have got not so promising values (for supply pulling, i.e. the PSRR @ DC and for phase noise). I thought that the main reason for the degradation is the different technologies and frequencies. At the time of the paper the output impedance of the transistors were much higher and there were bigger headroom for the signal swing.
If PSRR is a problem at low frequencies try to use cascode or self-cascode architecture for the load (or increase L). If it is a problem at high frequencies try to reduce the parasitic capacitances by reducing the size of the transistors (tail current source, and maybe the load).

The differential structure has an another benefit: the quadrature output is present without any excess circuit!

Good luck!

 

[wuxy]

symmetric load replica bias swing

i think u should to know the meanings of symmetric loads,u could search the paper "Low-Jitter Process-Independent DLL and PLL Based on Self-Biased Techniques" by John G. Maneatis...Besides, u should design another circuit(self-biased replica stage) to provide Vctrl and Vbias which the two voltage are dependent.If u do not produce the self-biases stage,the advantages of symmetric loads will be Vanished!!This paper is classical one in the oscillator. I suggest u reading it

Could you please provide this paper "Low-Jitter Process-Independent DLL and PLL Based on Self-Biased Techniques" for me? I have no IEEE account.Thanks!

 

[wuxy]

load ring calculations

i think u should to know the meanings of symmetric loads,u could search the paper "Low-Jitter Process-Independent DLL and PLL Based on Self-Biased Techniques" by John G. Maneatis...Besides, u should design another circuit(self-biased replica stage) to provide Vctrl and Vbias which the two voltage are dependent.If u do not produce the self-biases stage,the advantages of symmetric loads will be Vanished!!This paper is classical one in the oscillator. I suggest u reading it

Could you please provide this paper "Low-Jitter Process-Independent DLL and PLL Based on Self-Biased Techniques" for me? I have no IEEE account.Thanks!

I have got it.