is difficult to translate for me since there are different unit,spec of Δf/ΔVdd<1%
the psrr should be very good for this kind of VCO. How you set up your simulation deck for PSRR?
darkk said:If my memory serves me right, this kinda VCO's phase noise performance is OK but not that good, compared to other ringoscl-based VCO. Even in terms of the PSRR, it's not the best actually.
jcpu said:neoflash said
the psrr should be very good for this kind of VCO. How you set up your simulation deck for PSRR?
Yes, you are right:
Need help about how to simulate PSRR of PLL under lock,
what I have is silicon data...
Could you please provide this paper "Low-Jitter Process-Independent DLL and PLL Based on Self-Biased Techniques" for me? I have no IEEE account.Thanks!aicer said:i think u should to know the meanings of symmetric loads,u could search the paper "Low-Jitter Process-Independent DLL and PLL Based on Self-Biased Techniques" by John G. Maneatis...Besides, u should design another circuit(self-biased replica stage) to provide Vctrl and Vbias which the two voltage are dependent.If u do not produce the self-biases stage,the advantages of symmetric loads will be Vanished!!This paper is classical one in the oscillator. I suggest u reading it
I have got it.wuxy said:Could you please provide this paper "Low-Jitter Process-Independent DLL and PLL Based on Self-Biased Techniques" for me? I have no IEEE account.Thanks!aicer said:i think u should to know the meanings of symmetric loads,u could search the paper "Low-Jitter Process-Independent DLL and PLL Based on Self-Biased Techniques" by John G. Maneatis...Besides, u should design another circuit(self-biased replica stage) to provide Vctrl and Vbias which the two voltage are dependent.If u do not produce the self-biases stage,the advantages of symmetric loads will be Vanished!!This paper is classical one in the oscillator. I suggest u reading it
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