Here you go...
Clock nets being of higher frequency are more sensitive with regard to timing - transition rise, fall times etc. Hence clock buffers have equal rise and fall slew rates, On the other hand, normal buffers are designed with p/n ratio such that sum of rise delay and fall delay is minimum (atleast for high speed libraries)
Reason for doing this(symmetricity) is to prevent duty cycle of clock signal from changing when it passes through a chain of clock buffers.
Hope this helps!