ste2006
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Hi,
I have a new system developed using 5 SPI devices and am having major issues with it. After a large amount of testing over the past number of weeks the issue appears to be a brand new ST chip that is not setting its SDO line to high impedance when it has been De-Selected. It is always holding the line preventing any other chips controlling the bus. We have at this stage confirmed this is the issue but the next problem is how to solve it.
I was thinking something like tying a P channel FET to the Chip Enable so when the chip is not selected the SDO line will be disconnected from the main bus and when the chip is selected the FET will turn on and the chip can communicate.
I have seen similar examples for I2C using N Type FETs but can find nothing at all like what i want.
Anyone any thoughts or ideas on parts to look at. The SPI bus is being clocked at 1Mhz.
Thanks,
Stephen
I have a new system developed using 5 SPI devices and am having major issues with it. After a large amount of testing over the past number of weeks the issue appears to be a brand new ST chip that is not setting its SDO line to high impedance when it has been De-Selected. It is always holding the line preventing any other chips controlling the bus. We have at this stage confirmed this is the issue but the next problem is how to solve it.
I was thinking something like tying a P channel FET to the Chip Enable so when the chip is not selected the SDO line will be disconnected from the main bus and when the chip is selected the FET will turn on and the chip can communicate.
I have seen similar examples for I2C using N Type FETs but can find nothing at all like what i want.
Anyone any thoughts or ideas on parts to look at. The SPI bus is being clocked at 1Mhz.
Thanks,
Stephen