hi, i am having a pll operating at the range 1-500 Mhz. I have designed pmos and nmos switches but the output of the switches is wrong. can anyone help me about which parameter should i change in the pmos and nmos switches so that i get right output. is it the w/l ratio? or anyother parameter
Please elaborate on what you mean by "the output is wrong".
Please post your CP schematic.
What about your phase detector? Is it a PFD? Have you verified that this is working correctly i.e. you're sure the only
part of the loop not working is the CP?