Ive never seen one before. From googling, trireg was meant to be used for modelling capacitive networks. If it's in some code for an FPGA - sack the coder. If all the drivers are 1'bz, then it retains whatever the last value was (other than Z).
This is obviously someone thinking trireg means "tri-state register". Incorrect. This can be modelled with a simple reg or logic type.
In SV, variable types are far more inter-changable. Just ignore silly things like trireg and any analogue modelling stuff.