some_jagged_array ( 0 to 7 ) ( array_of_integers_to_set_the_width ( index ) - 1 downto 0 )
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 type slv_array_t is array(natural range <>) std_logic_vector; type slv_array_ptr_t is access slv_array_t; type jagged_array_t is array(natural range <>) of slv_array_ptr_t; variable jagged_array : jagged_array_t(0 to 7); .... jagged_array(0) := new slv_array_t(0 to 2)(31 downto 0); jagged_array(1) := new slv_array_t(0 to 100)(0 to 7); -- etc
Code Verilog - [expand] | |
1 2 3 4 | bit [31:0] some_jagged_array [8][]; parameter int array_of_integers_to_set_the_width[8] = {8,7,6,5,7,8,9,4}; foreach (some_jagged_array[dim1st]) some_jagged_array[dim1st] = new[array_of_integers_to_set_the_width[dim1st]]; |
entity mother is
generic
(
array_of_integers ( 0 to 7 )
)
port
(
jagged_output_ports ( 0 to 7 )
)
end entity ;
architecture rtl_mother of mother is
component daughter is
generic
(
width : positive
)
port
(
some_output : std_logic_vector ( width - 1 downto )
) ;
end component daughter ;
begin
create_8_daughters_width_different_output_widths : for index in 0 to 7
generate
iterate_8_times : daughter
generic map
(
width => array_of_integers ( index )
)
port map
(
some_output => jagged_output_ports ( index )
) ;
end generate ;
end architecture rtl_mother ;
TrickyDicky,
This is for synthesis - so I don't think using the access type is viable. But perhaps I'm wrong...
I'll explain what I want to do.
Component "daughter" is instantiated inside entity "mother" as follows:
Can you please show an example.You can use a record type and a function that takes that record type, an x index, a y index, and returns an element.
Can you please show an example.This could possibly also be implemented with an array and an address conversion function.
Can you please show an example.
Can you please show an example.
This is not directly supported, but can be emulated. You can use a record type and a function that takes that record type, an x index, a y index, and returns an element.
This could possibly also be implemented with an array and an address conversion function.
This is exactly it...me learning.no. learn vhdl.
1. Using a flat vector instead of an array - which IMO makes for a really ugly unreadable code.
An example would be having a lookup table of the cumulative sum of the widths of the x indicies. eg, if the jagged array has a 5 element array, a 7 element array, and an 8 element array then you could have a lookup table with 0, 5, 5+7, 5+7+8. The total size of the array is 5+7+8 = 20. The lookup function is lut(x) + y, eg f(0, 3) gets the element at index 3 from the 5 element array (0 + 3). f(1, 2) gets index 2 from the 7 element array. (5 + 2). f(2,7) gets index 7 from the 8 element array (5+7 + 7).
But this will still leave you with a bunch of unused logic to be optimized away - right ?
port map
(
some_output => packedOutputPort ( kCSum(i+1)-1 downto kCSum(i))
) ;
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