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Simple..
Connect a ideal Voltage Source to Vtune and do a PSS-PNOISE analysis then Connect a Vnoise in series to this Ideal Voltage Source ( or attribute a Noise Voltage value in related field) then do the same simulation then compare these two results.You will find the "sensitivity" of the VCO against Noise Contribution.
You can also add/subtract Noise Voltage Source to Vcc to find Supply Sensitivity of the VCO.
yep, what he said.
or you can add a AC signal, say 10 mV at a fixed single frequency (10 Hz to 1 MHz), and look at the VCO output and find a double sideband phase modulation spur that that bias caused. take a few different bias frequencies, and you can convert that discrete spur level into an approximation of resulting phase noise
you want to try a bunch of frequencies for the bias noise, as there may be active feedback mechanisms inside the chip that suppress the incoming ripple. Also try adding external bias line capacitors to your modelling, to see just how much passive suppression you can get. Often, you are stuck with a fixed amount of ripple on the bias line, due to the use of switching voltage regulators in the system. adding external R-C bias filters can help a lot, especially above 100 KHz offset from the carrier, where active regulation starts to fail
Simple..
Connect a ideal Voltage Source to Vtune and do a PSS-PNOISE analysis then Connect a Vnoise in series to this Ideal Voltage Source ( or attribute a Noise Voltage value in related field) then do the same simulation then compare these two results.You will find the "sensitivity" of the VCO against Noise Contribution.
You can also add/subtract Noise Voltage Source to Vcc to find Supply Sensitivity of the VCO.
Close-in phase noise is the usual interest, meaning
low frequency noise from individual devices is the
likely problem (0.01 - 1kHz). Make the sine source
frequency a variable and step through it by octaves,
from near zero to at least your channel "mask" width.
That would be what you'd assume is required for
spurious emissions, unless told otherwise.
100kHz switcher noise may put spurs out-of-band,
or not, depending on how tightly the channels are
packed. Switcher ripple is something that can be
measured, while device noise can only be modeled
as a practical thing (have you or have you not, a
proper noise measurement cabinet, clean samples
of individual devices in various geometries, and the
time*talent to fit the models (while you were likely
supposed to be getting on with the designing?)?
Depending on application you might want to look
at the problem in other ways. For example a clock
recovery PLL is not really interested in small signal
phase noise, but large signal jitter and would be
better analyzed by marching impulses that represent
supply noise (as characterized or as spec'd) across
the phase comparator crossing event in time domain,
to get an eye diagram. Impulses imposed on the tune
line are not necessarily helped by the loop amp with
its low bandwidth,
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