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suitable start-up circuit for designing high PSRR BGRs

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jamaleddin mollasalmani

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Hello to all

I wanna know if someone can help me to find a suitable start-up circuit for designing high PSRR BGRs?

Or better i say ,does start-up circuit affect PSSR of BGR?

Thanks.
 
Last edited:

Hi erikl,

could you clarify your answer!

As i know start-up circuit will go off immediately after making circuit to work and as transient time it will take some micro seconds to have output voltage ,so start-up circuit will go off after start of main crcuit not after reaching output voltage.

Also in most of circuits Start-up does not include just one element.may be included of number of Mosfets which after running main circuit they will still be on but the last element which force main circuit to work will go off, so it is not necessary for a start-up circuit to be totally off.

I will be glad if you discuss on my points.

Thanks
 
Last edited:

As i know start-up circuit will go off immediately after making circuit to work and as transient time it will take some micro seconds to have output voltage ,so start-up circuit will go off after start of main crcuit not after reaching output voltage.

That's why the start-up switch-off time should depend on the (stable) output voltage, not on an RC time constant. The latter method has the disadvantage of possibly not working correctly, when the BGR cell is switched on again immediately after being switched off, because the cap is still charged.

Also in most of circuits Start-up does not include just one element.may be included of number of Mosfets which after running main circuit they will still be on but the last element which force main circuit to work will go off, so it is not necessary for a start-up circuit to be totally off.

A MOSFET which still is on after start-up time shouldn't be connected directly to the proper BGR circuit, but via a further device (MOSFET), which then is totally off.
 

Start-up circuit should be totally off after BGR output voltage is reached. Then its impedance is much higher than that of other devices connected to the power supply rails.

This is preferable, but a lot of the older art is not that
way; you'll simple diode current density steering in the
old bipolar technologies, which can be only a hundred mV
away from really jacking the output voltage and can
contribute HF PSRR easily, when you care about more
than 7-8 bits.

A "digital" switch scheme to suppress boot current will
give you more margin against that kind of thing. But it
may not have the "free tracking" of diode-vs-diode
steering, giving you trouble at extremes of temp and/or
process if you were to (say) just put VBG to the gate
of a NMOS transistor to derive your "done booted" term.

Your choice of where to take the startup current from,
and what to pas it through, determines to large extent
your HF PSRR - where do all those stray Cdb, Cdg terms
return, and what happens when that point is jumping
relative to the sensitive bandgap core destination point?

To that end you may find a need to add cascodes just
for quietness, etc. which of course adds more headroom
and opportunity for "discovery".
 

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