sagar_echip
Newbie level 6

verilog based project
pls. suggest me a verilog based reference design(project) which explains all the
steps from specification to synthesis, for study purpose.
medium sized project in networking domain will be preferable
i know opencores.org
thanks
pls. suggest me a verilog based reference design(project) which explains all the
steps from specification to synthesis, for study purpose.
medium sized project in networking domain will be preferable
i know opencores.org
thanks