I am using 6C-Cc-6C split array and you know, running through 4096 steps in transient simulation to check INL/DNL is taking much time and some faster simulator is required, like HS*M or Nanos*m, from those simulators, it's not easy to get perfect results and that's why I said, even not good in simulation. if on the other hand, simulate with a 1Khz sine wave to get SNR maybe a good choice.
What have u done for your ADC? Let's share
Did u play around more than 12b? I mean 14b or 16b, Not more than 16b for SARADC as it is not quite useful for applications, if more than 16b, I prefer SDADC since it is much standardized and easier compare to 16b SARADC without much literatures talking about how to do that?
What kind of comparators you did use in your design ?