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Substrate current is a measure of hot electrons injected into the Wells during worst case conditions between gate and drain voltages, for hot electron generation at the drain. If the substrate current is high, then it is generally considered that hot electrons are also being injected into the gate and degrading the quality of the oxide causing threshold shifts and Gm degradation over time. This is called hot carrier injection or HCI. Every Fab process will have a quality specificqtion that the Gm will not degrade worse than 10% over 10 years of operation and worst case conditions. Most Fabs far exceed this and for pmos, may well surpass 100 years before the degradation is seen.
For analogue applications, it has severe impact on matching if the transistors become degraded.
Another hidden effect is when the Wells are not adequately contacted to Vss or Vdd.
Substrate current (possibly from an unrelated source) can change the actual Well bias close to critical transistors but far from the Well tap connections. This causes their Vts to change during the substrate current event. This can be very hard to trace as it is a "soft failure" i.e. it does not happen all the time.
there is always a substrate current in MOSFET. The explanation by Colbhaidh is correct. Substrate current will cause Reliability issue of the transistor by changing Vt.
Added after 2 minutes:
bicave said:
High electrical field between Drain-Source cause collssion and generate electron, the phenomenon is hot carrier. Some electrons go to substrate.
High electric field will generate electron-hole pair at the drain. The electron will be injected into oxide while the hole will be swept into substrate. So, substrate current is caused by hole (NMOS) not by electron.
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