Sub threshold SRAM design

Status
Not open for further replies.
A

arunramnath

Junior Member level 1
Joined
Apr 2, 2010
Messages
15
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Location
Austin
Activity points
1,386
Hello friends,

I am currently working on sub-thresold sram design for my thesis. I do not find any recent papers on this topic. I just want to know whats the scope of research on this field.

I have been working for a new design for the past 2 months, but nothing satisfactorey is up. Also, I do not find enough papers on this topic. So, please help me.
 

See this thread. The designated book contains a paragraph (7) on "Sub-threshold Memories" and (7.2) "Sub-threshold SRAM" (pp. 115 .. 146).
 
how can I calculate the read SNM of the 10T sram used in thebook?

normally i can make a DC sweep on one of the storage nodes and plot the change in case of reading in a 6T sram.. but how can I do for the 10T sram as shown in the thread given above?
 

I'm not at all an SRAM expert, sorry (bought the book just on general interest in sub-threshold design).
However, I guess you could use the same method as for the 6T cell. The 2 inverters essentially are responsible for holding the data; the 4 more transistors just care for less loading / better separation, isn't it?
 

Status
Not open for further replies.

Similar threads

Menu
Log in
Register
Cookies are required to use this site. You must accept them to continue using the site. Learn more…