Structures for power on reset circuits

[ambreesh]

Re: Power on reset

The power supply for the BGR and the POR are same.
Assume that your supply is 2.5V, then your BGR should become operational at VDD of 2V.
As for comparator with internal hystersis, you should go through Comparator chapter of Allen Holberg. If you have any doubts we can discuss it.

 

[ccw27]

Re: Power on reset

A Schmitt trigger after a comparator can also do the job. Check Rabaey or Baker

 

[incol]

Re: Power on reset

The power supply for the BGR and the POR are same.
Assume that your supply is 2.5V, then your BGR should become operational at VDD of 2V.
As for comparator with internal hystersis, you should go through Comparator chapter of Allen Holberg. If you have any doubts we can discuss it.

when supply is 1v,then BGR doesnt work and its output is 0,so comparator's input are 1v and 0v,and comparator's output is a high level

 

[woodman]

Power on reset

I also have a question:
How to design a easiest POR circuit?
I just want to detect the supply voltage!
For example: If supply lower than 2.5±0.1V, POR signal generate.
BGR and Comparator are enough?

Thanks!

 

[ambreesh]

Re: Power on reset

Dear Incol,
For what VDD are u developing the POR, then we can take the discussion forward from their.
Also BGR output would not be zero for Vdd of 1V but would be following it.

For the simplest circuit, go to this

 

[venkateshr]

Re: Power on reset

Hi,

I have one . POwer ----- Resistor_small----|------------CMOS_BUFFER---Reset_ckt
| |
CAP Resistor_huge
---------GND

 

[incol]

Re: Power on reset

Dear Incol,
For what VDD are u developing the POR, then we can take the discussion forward from their.
Also BGR output would not be zero for Vdd of 1V but would be following it.

For the simplest circuit, go to this
h**p://

my design requests that when vin is low, output is hign level, and when vin over threshold, then output become low level. for example if vin=vdd=0, vout should 5v , but if there isnt another stable voltage,how can 0v voltage bring a 5v voltage?

 

[ambreesh]

Re: Power on reset

Dear Incol,
High here would refer to a high impedance node.
So the output should have a NMOS open drain configuration.
find 2 files attached, i hope they would help u

 

[wuwuwengong]

Power on reset

dear ambreesh:
could you tell me the structure of the comparator with internal hystersis, i had design one comparator with internal hystersis, but the high level was only 1v.

 

[ambreesh]

Re: Power on reset

Dear wuwuwengong,
If you have allen holberg, please refer to page #471 fig 8.4-11.
He has explained it very nicely.
If you still have any doubts we can discuss and clear it

 

[incol]

Re: Power on reset

Dear Incol,
High here would refer to a high impedance node.
So the output should have a NMOS open drain configuration.
find 2 files attached, i hope they would help u

dear ambreesh
but i dont understand when vin(vcc)=0v,how can vout=5v,if there isnt any other voltage source?

 

[jay_ec_engg]

Re: Power on reset

You can implement the reset counter inside some programable device like PLD. It will give you flexible timing solution as per ur requirment. This is the method which ppl use nowadays..

 

[ambreesh]

Re: Power on reset

Dear Incol,
I agree that we cannot get 5V, when one is not their.
Wiht that open drain NMOS do you have path to ground when Vin=0.
The output of the open drain is usually connected via a pull up resistor to the VDD.
In that case you should have another supply.

 

[wuwuwengong]

Power on reset

is there anyone who have this papaer “A
Precision CMOS Double-Sided Power-On-Reset Circuit for the
1.8V Power Supply,” by Wen-Cheng Yen, Yu-Tong Lin, Hung-wei Chen,
i had searched it ,but can`t download it. Could you help me?