BlackOps
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-- define the operation of the 2-input NAND gate
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY NAND_2 IS PORT (
I0, I1: IN STD_LOGIC;
O: OUT STD_LOGIC);
END NAND_2;
ARCHITECTURE Dataflow_NAND2 OF NAND_2 IS
BEGIN
O <= I0 NAND I1;
END Dataflow_NAND2;
-- define the operation of the 3-input NAND gate
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY NAND_3 IS PORT (
I0, I1, I2: IN STD_LOGIC;
O: OUT STD_LOGIC);
END NAND_3;
ARCHITECTURE Dataflow_NAND3 OF NAND_3 IS
BEGIN
O <= NOT (I0 AND I1 AND I2);
END Dataflow_NAND3;
-- define the operation of the SR input block to the D flip-flop
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY SRin IS PORT (
R, S, Q: IN STD_LOGIC;
D: OUT STD_LOGIC);
END SRin;
ARCHITECTURE Dataflow_SRin OF SRin IS
BEGIN
D <= (Q AND (NOT R)) OR S ;
END Dataflow_SRin;
-- define the structural operation of the SR latch
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY SRlatch IS PORT (
SN, RN: IN STD_LOGIC;
Q, QN: BUFFER STD_LOGIC);
END SRlatch;
ARCHITECTURE Structural_SRlatch OF SRlatch IS
COMPONENT NAND_2 PORT (
I0, I1 : IN STD_LOGIC;
O : OUT STD_LOGIC);
END COMPONENT;
BEGIN
U1: NAND_2 PORT MAP (SN, QN, Q);
U2: NAND_2 PORT MAP (Q, RN, QN);
END Structural_SRlatch;
-- define the structural operation of the SR flip-flop
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY SR-FF IS PORT (
S, R, Clear, Clock: IN STD_LOGIC;
Q : BUFFER STD_LOGIC);
END SR-FF;
ARCHITECTURE Structural_SR-FF OF SR-FF IS
SIGNAL N1, N2, N3, N4, N5: STD_LOGIC;
COMPONENT SRlatch PORT (
SN, RN: IN STD_LOGIC;
Q, QN: BUFFER STD_LOGIC);
END COMPONENT;
COMPONENT NAND_2 PORT (
I0, I1: IN STD_LOGIC;
O: OUT STD_LOGIC);
END COMPONENT;
COMPONENT NAND_3 PORT (
I0, I1, I2: IN STD_LOGIC;
O: OUT STD_LOGIC);
END COMPONENT;
COMPONENT SRin PORT (
S, R, Q: IN STD_LOGIC;
D: OUT STD_LOGIC);
END COMPONENT
BEGIN
U1: SRlatch PORT MAP (N4, Clock, N1, N2, Clear); -- set latch
U2: SRlatch PORT MAP (N2, N3, Q, QN, Clear); -- output latch
U3: NAND_3 PORT MAP (N2, Clock, N4, N3); -- reset latch
U4: NAND_2 PORT MAP (N3, N5, N4, Clear); -- reset latch
U5: SRin PORT MAP (S, R, Q, N5); -- SR INPUT
END StructuralDFF;
process(C,Clear)
begin
if (Clear) then
Q <= '0';
elsif (rising_edge(C)) then
if (R = '1') then
Q <= '0' ;
elsif (S = '1') then
Q <= '1' ;
end if;
end if;
end process;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY SRff IS PORT (
S, R, Clock, Clear: IN STD_LOGIC;
Q: OUT STD_LOGIC);
END SRff;
ARCHITECTURE Behavior OF SRff IS
BEGIN
PROCESS(Clock, Clear) -- sensitivity list is used
BEGIN
IF (Clear = '1') THEN
Q <= '0';
ELSE
IF Clock'EVENT AND Clock = '1' THEN
IF (R = '1') THEN
Q <= '0';
ELSIF (S = '1') THEN
Q <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END Behavior;
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