LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY FIFO_tb IS
END FIFO_tb;
ARCHITECTURE behavior OF FIFO_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT Asynch_FIFO
PORT(
rst : IN std_logic;
wr_clk : IN std_logic;
rd_clk : IN std_logic;
din : IN std_logic_vector(7 downto 0);
wr_en : IN std_logic;
rd_en : IN std_logic;
dout : OUT std_logic_vector(7 downto 0);
full : OUT std_logic;
empty : OUT std_logic;
rd_data_count : OUT std_logic_vector(7 downto 0);
wr_data_count : OUT std_logic_vector(7 downto 0)
);
END COMPONENT;
--Inputs
signal rst : std_logic := '0';
signal wr_clk : std_logic := '0';
signal rd_clk : std_logic := '0';
signal din : std_logic_vector(7 downto 0) := (others => '0');
signal wr_en : std_logic := '0';
signal rd_en : std_logic := '0';
--Outputs
signal dout : std_logic_vector(7 downto 0);
signal full : std_logic;
signal empty : std_logic;
signal rd_data_count : std_logic_vector(7 downto 0);
signal wr_data_count : std_logic_vector(7 downto 0);
-- Clock period definitions
constant wr_clk_period : time := 10 ns;
constant rd_clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: Asynch_FIFO PORT MAP (
rst => rst,
wr_clk => wr_clk,
rd_clk => rd_clk,
din => din,
wr_en => wr_en,
rd_en => rd_en,
dout => dout,
full => full,
empty => empty,
rd_data_count => rd_data_count,
wr_data_count => wr_data_count
);
-- Clock process definitions
wr_clk_process :process
begin
wr_clk <= '0';
wait for wr_clk_period/2;
wr_clk <= '1';
wait for wr_clk_period/2;
end process;
rd_clk_process :process
begin
rd_clk <= '0';
wait for rd_clk_period/2;
rd_clk <= '1';
wait for rd_clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
RST <= '1';
wait for Wr_clk_period;
RST <= '0';
wait for Wr_clk_period;
for i in 0 to 255 loop
Wr_en <= '1';
wait for Wr_clk_period;
din <= din + 1;
end loop;
for i in 0 to 255 loop
Wr_en <= '0';
Rd_en <= '1';
wait for Rd_clk_period;
end loop;
-- insert stimulus here
wait;
end process;
END;