stm32f4 discovery interface with wiznet w5300

[samandj15]

anyone knows how to drive w5300 Ethernet chip from stm32f4 discovery?

i think (w5300 / wiz830mj module) can be controlled through DMA (direct media access) / FSMC (flexible static memory controller) like external Sram, but i don't know how to implement DMA and FSMC in stm32f4 discovery

take a look at hardware connection in attached image, FSMC routines, wiznet w5300 drivers and libraries, w5300 datasheet from wiznet:

#define Bank1_SRAM1_ADDR ((uint32_t)0x60000000)

#define BAZA_WIZ ((u32)0x60000000)

//непосредственно переключение адресной линии. это FSMC делает сам

#define IDM_AR0 ((u32)BAZA_WIZ + 0x00010000)

#define IDM_AR1 ((u32)BAZA_WIZ + 0x00020000)

#define IDM_DR ((u32)BAZA_WIZ + 0x00030000)



//Reset Wiznet

#define reset_ON() GPIOC->BRR = GPIO_Pin_5

#define reset_OFF() GPIOC->BSRR = GPIO_Pin_5



FSMC_NORSRAMInitTypeDef FSMC_NORSRAMInitStructure;

FSMC_NORSRAMTimingInitTypeDef p;



/*-- GPIO Configuration ------------------------------------------------------*/



/*!< SRAM Data lines configuration */

GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_14 | GPIO_Pin_15;

GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;

GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;

GPIO_Init(GPIOD, &GPIO_InitStructure);



GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7 | GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10;

GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;

GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;

GPIO_Init(GPIOE, &GPIO_InitStructure);





/*!< SRAM Address lines configuration */

//A16 - pin 11

//A17 - pin 12

GPIO_InitStructure.GPIO_Pin = GPIO_Pin_11 | GPIO_Pin_12;

GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;

GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;

GPIO_Init(GPIOD, &GPIO_InitStructure);





/*!< NOE and NWE configuration */

GPIO_InitStructure.GPIO_Pin = GPIO_Pin_4 | GPIO_Pin_5;

GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;

GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;

GPIO_Init(GPIOD, &GPIO_InitStructure);



/*!< NE1 configuration CS chip select*/

GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7;

GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;

GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;

GPIO_Init(GPIOD, &GPIO_InitStructure);



/*!< INT configuration flag*/

GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0;

GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;

GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;

GPIO_Init(GPIOB, &GPIO_InitStructure);



/*Reset Wiznet configuration*/

GPIO_InitStructure.GPIO_Pin = GPIO_Pin_5;

GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;

GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;

GPIO_Init(GPIOC, &GPIO_InitStructure);



/*-- FSMC Configuration ------------------------------------------------------*/



p.FSMC_AddressSetupTime = 3;



p.FSMC_AddressHoldTime = 2;



p.FSMC_DataSetupTime = 3;



p.FSMC_BusTurnAroundDuration = 1;



p.FSMC_CLKDivision = 1;



p.FSMC_DataLatency = 0;



p.FSMC_AccessMode = FSMC_AccessMode_A;



FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM1;

FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;

FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_SRAM;

FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b; //8-bit Wiznet DATA line

FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;

FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;

FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;

FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable;

FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;

FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable;

FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable;

FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;

FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable;

FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p;

FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p;



FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure);



/*!< Enable FSMC Bank1_SRAM Bank */

FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM1, ENABLE);



RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOD | RCC_APB2Periph_GPIOC | RCC_APB2Periph_GPIOB | RCC_APB2Periph_GPIOE | RCC_APB2Periph_AFIO, ENABLE);

RCC_AHBPeriphClockCmd(RCC_AHBPeriph_FSMC, ENABLE);





NVIC_InitTypeDef NVIC_InitStructure;



#ifdef VECT_TAB_RAM

/* Set the Vector Table base location at 0x20000000 */

NVIC_SetVectorTable(NVIC_VectTab_RAM, 0x0);

#else /* VECT_TAB_FLASH */

/* Set the Vector Table base location at 0x08000000 */

NVIC_SetVectorTable(NVIC_VectTab_FLASH, 0x0);

#endif



/* Enable the FSMC global Interrupt */



NVIC_PriorityGroupConfig(NVIC_PriorityGroup_2);

NVIC_InitStructure.NVIC_IRQChannel = FSMC_IRQn;

NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;

NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;

NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;

NVIC_Init(&NVIC_InitStructure);

thanks in advance