when RTL is written, They would assume that , data will be passed between the registers, with respect to clock edges, i,e one edge launches data on q pin of ff then by next edge only the next ff should capure/read it.
setup time check makes sure that, when next clk edge reaches the ff2, data will be ready at the ff d pin, if its not ready before clk arrives, then flop may go to metastability mode, where we can't assure the o/p of the flop.
hold time assueres that , the launched data from ff1 will not be caputre in the same edge of the clok