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Stepper motor control with fsm

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Toyona Entwined

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Hello~

We were given an assignment in class where we have to design an fsmd to control a stepper motor, draw the asm charts, hardware architecture, write the code in System Verilog along with test-benches and lastly, simulate it. The task is divided into 3 parts, where the 1st one involves moving a stepper motor 10mm right (it follows a pattern of 1010, 1001, 0101, 0110 for clockwise rotation and backwards for counter-clockwise so we have to assume after completing the pattern once, it makes a 360 degree rotation and moves 1mm right/left) and then 4mm backward. I have tried drawing the asm chart and the architecture but I'm not sure if Im right so I havent written the code yet. I believe 2 counters will be required in the datapath for this-the 1st of which hold the state for 10 clock cycles here and the 2nd counter (CNT2_LT_10 then CNT2_LT_14) the counter which checks whether the motor has followed the whole pattern 10 times for moving 10mm forward...and then checks again for 4mm backward. But how exactly do I put the SCLR signal here? Wont SCLR clear both the counters according to what I have drawn? Or is there another way...?

Thanks~

Images:
https://obrazki.elektroda.pl/1965193200_1416286443.jpg
https://obrazki.elektroda.pl/9223530100_1416286446.jpg
https://obrazki.elektroda.pl/1140703300_1416286448.jpg
https://obrazki.elektroda.pl/6276315200_1416286450.jpg
 

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