Steady state error between type 1 and type 2 compensator

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Patrick_66

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Hello everyone,

Currently I'm trying to simulate an LED driver with flyback configuration in DCM mode.
The output current is around 0.7A with 18W output power.

The problem that I'm currently facing is that the time to reach steady state is higher when using a type 3 compensator compared to a type two compensator. Wanted to know whether this is normal or wrong because if not mistaken using type 3 compensator is better for the overall performance of the system.

The system has a phase margin of 90 degrees when using a type 2 compensator whereas the phase margin is around 125 degrees when using a type 3 compensator and both having the same cross-over frequency. The figure of the circuit and simulation is shown below.

Hope that you can enlighten me and correct my mistake.
Thank you in advance for the help.



 

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Hello Sir, as of now does my simulation make sense? Is it normal to have a system which longer transient response for type 3 compensator compared to type 2 compensator?
 

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Type II and Type 3 can both be designed to tradeoff speed and for settling time
to some final value. Designer determines what results they want. A lead lag (Type III)
compensator can improve both speed and steady state, again designer
chooses that by positioning pole-zeros.


Fundamentals of Lead and Lag Compensators

This is now my third post on designing lead and lag compensators (I wrote a post on lead compensators, and a summary of lead, lag and lead-lag compensators. I am finding controller design to be the most challenging concept that I have encountered so far in studying classical control theory. I...
sassafras13.github.io


Regards, Dana.
 
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Estimate the Poles from your RC=Tau (T) values and compare. Your two Types examples, I think do not use the same values.
A larger T for the partial integrator will increase settling time. Choosing filter response with critical damping (Butterworth) or no overshoot (Bessel) or higher BW ( faster response time) as maybe a way to set your goals. These are also tradeoffs with stability, step response error or interference error. This is the same as the methods to compute optimal PID constants Kp, Ki, Kd. Generally ultra-low ESR is a critical factor for ripple with gain which affects filter pole for optimal results. You get to define between what is optimal and what is possible.

This is a not an answer, but a heads-up on how to analyze your filter with different methods for time and frequency domain (Bode or Root Loci)
 
Last edited:
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Hello sir i use this way to analyse the compensator with the transfer function of the flyback with PWM. Is this the correct way of doing it?
 

Attachments

  • Type 2 Diagram.png
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  • Type 2 error.png
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  • Type 2 Freq Response.png
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  • Type 2 Waveform.png
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  • Type 3 diagram.png
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  • type 3 Error.png
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  • Type 3 Freq Response.png
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  • Type 3 Waveform.png
    67.7 KB · Views: 34

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