procedure registery(signal clock : in std_logic;
signal rst : in std_logic;
signal input : in std_logic_vector;
signal output : out std_logic_vector)is
begin
if rst = '0' then
for i in output'range loop
output(i) <= '0';
end loop;
elsif rising_edge(clock) then
output <= input;
end if ;
end procedure registery ;
what is the syntex for assigning to it std_logic (not vector)
The problem here is that its a procedure - and on a precedure object classes must match.
So while constants can be connected to anything, signals must connect to signals and variables must connect to variables.
The original concatenation I suggested creates a constant.
unlikely to work, as output from the procedure has no length, and is sized from the slv that is connected.
To the OP, you will need a slv signal to connect to - so you'll need a temporary signal to connect to, and then connect a single bit to your std logic.
Surprisingly, Modelsim accepts the partial association, both for procedures and components.
Quartus does for components, but doesn't support partial association for procedures.