States reduction techniques

[dammadmin]

Hello everyone. I study a module on Electronic Sytem Design. Its all about digital electronics. so here is my question:

Under what conditions can we use row matching method or implication matrix(chart) method in order to reduce the number of states in Finite State machines ( both completely specified and incompletely specified) .???

any help much appreciated.. thanks in advance..

 

[vlsi_freak]

Please refer Digital design by John Wakerly.
Its a good book for this topic.

Hope it helps.

regards,
freak

 

[dammadmin]

Thanks for your advice. i will check in the book. any other suggestions?

 

[pmat]

Hi,
the problem is much easier for completely specified machines. If you
are interested in the EDA algorithms check chapter 7 section 4 of :
https://www.amazon.com/Logic-Synthesis-Verification-Algorithms-Hachtel/dp/0792397460
With respect to incompletely specified FSMs then study chapter 8 of the
same book. It is more or less, the theory behind FSM minimization
of the Synthesis tools today...

Pavlos