State Machine with VHDL

entity load_mode is

	port(clk1, reset, t, we, mode: in std_logic; --to controle the load----
			
	
			dins1,dins2: out std_logic_vector(11 downto 0));---to stock the coefficients---

end load_mode;

architecture Behavioral of load_mode is

signal i: integer range 0 to 31;
signal j: integer range 0 to 55;
type state_type is (s0,s1); -- type of state machine
signal current_s,next_s: state_type; --current and next state declaration

begin

	process(clk1, reset, mode)
		begin
			if (reset='1') then
				current_s <= s0; -- default state on reset
				dins1 <= "000000000000";
				dins2 <= "000000000000";
				i<=0;
				j<=0;
				
			elsif(rising_edge(clk1)) then
				current_s <= next_s;
				if (we='1') then
					if (mode='0') then ---mode0 => 80 MHz-----
						if (i <= 30) then						
						dins1<=dins1_reg0(i);---load the coefficients one by one---
						dins2<=dins2_reg0(i);
						
						i<=i+1;
						else ---stop the incrementation of i----
						dins1<=dins1_reg0(i);
						dins2<=dins2_reg0(i);
						
						end if;
						
					else----mode1 => 32 MHz------
						if (j <= 54) then
						dins1<=dins1_reg1(j);
						dins2<=dins2_reg1(j);
						
						j<=j+1;
						else ---stop the incrementation of j----
						dins1<=dins1_reg1(j);
						dins2<=dins2_reg1(j);
						
						end if;
					end if;
				end if;
			end if;
		end process;