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State machine is not working as expected

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Maxwell077

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Hi;

I have observed unusual behavior in my state machine.
Let me explain what's happenning.

I have 6 states and they are one-hot encoded by synthesis tool.

idle : 000001
2nd_st : 000010
3rd_st : 000100
4th_st : 001000
5th_st : 010000
6th_st : 100000

After reset, state goes to idle(000001), and pulled down reset pin state goes to 2nd_st and waits for interrupt.
After interrupt is occured, state goes to unknown and un-encoded state - "000000" and waits there forever.
There is "others" clause in my code and normally state should be directed to idle, but it is not.

I couldn't find any reason why state goes to unknown state. Code is not working because of this issue.

Any help would be appriciated.

Thanks

Code:
process(ft245ClkOut)
    begin
        
        if falling_edge(ft245ClkOut) then
            
            if syncRst = '1' then
                currState       <= idle;              
                s_pixel_wdata   <= (others => '0');
                pre_pixel_we    <= '0';
            else
                pre_pixel_we    <= pixel_we;
                case currState is
                
                    when idle =>
                        currState       <= checkForPixelRdy;
                        s_pixel_wdata   <= (others => '0');
                        pre_pixel_we    <= '0';
                        
                    when checkForPixelRdy =>
                        if pre_pixel_we = '0' and pixel_we = '1' then
                            currState       <= checkForTxBuff;
                            s_pixel_wdata   <= pixel_wdata;
                        else
                            currState <= checkForPixelRdy;
                        end if;
                        
                    when checkForTxBuff =>
                        if ft245TxFull = '0' then
                            currState <= sendPixelBigEndian;
                        else
                            currState <= checkForTxBuff;
                        end if;
                        
                    when sendPixelBigEndian =>
                        currState <= writeDone;
                        
                    when writeDone =>
                        
                        currState <= sendPixelLittleEndian;
                       
                    when sendPixelLittleEndian =>
                        currState <= checkForPixelRdy;
                        
                    when others =>
                        currState       <= idle;
                        s_pixel_wdata   <= (others => '0');
                        pre_pixel_we    <= '0';
                        
                end case;
            end if;
        end if;
    end process;
 

The most popular cause to get illegal states in FSM is that input signals are asynchronous to the state machine clock and not synchronized properly before being used to switch states.

Consider that every register bit of the state variable is sampling input signals independently. Assuming some delay skew in the logic implementation, one state bit might be reset without setting a new one.

There is "others" clause in my code and normally state should be directed to idle, but it is not.
Wrong expectaction. Non-existing ("illegal") states aren't handled by the others statement, because they are removed during design optimization, unless your synthesis tools supports a safe state machine feature handling illegal states. Altera Quartus e.g. does.
 

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