[SOLVED] 'state is unconnected in block' verilog code error

[arishsu]

Hi
I wrote a code for pulse generator. But it shows the following warnings.

WARNING:Xst:647 - Input <x> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:737 - Found 1-bit latch for signal <L>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:2677 - Node <2> of sequential type is unconnected in block <next_state>.
WARNING:Xst:2677 - Node <state_2> of sequential type is unconnected in block <pulse_generator>.
WARNING:Xst:2677 - Node <state_2> of sequential type is unconnected in block <pulse_generator>.
WARNING:Xst:2677 - Node <next_state_2> of sequential type is unconnected in block <pulse_generator>.

My code is given below

module pulse_generator(clk,reset,s,x,P,L);
input clk,reset,s,x;
output reg P,L;
localparam s0=00,
			 s1=01,
			 s2=10,
			 s3=11;
reg [1:0]state;
reg [1:0]next_state;
initial state<=s0;
always@(negedge clk)
begin
	state<=next_state;
end
always@(negedge clk or posedge reset)
 begin
	if(reset)
	 next_state<=s0;
	else
	begin
	 case(state)
	  s0: begin
				if(s==1)
					next_state<=s1;
				else if(s==0)
					next_state<=s0;
			end
	  s1: begin
			if(s==1)
				next_state<=s2;
			else if(s==0)
				next_state<=s0;
			end
	  s2: begin
			if((s==1)&&(x==0))
				next_state<=s3;
			else if((s==1)&&(x==1))
				next_state<=s1;
			else if(s==0)
				next_state<=s0;
			end
	  s3: begin
			if((s==1)&&(x==1))
				next_state<=s1;
			else if((s==1)&&(x==0))
				next_state<=s3;
	      else if(s==0)
				next_state<=s0;
			end
	 endcase
 end
 end
always@(state)
begin
	case(state)
	 s0:begin
			P=0;
			L=0;
		 end
	 s1:begin
			P=1;
			L=1;
		 end
	 s2:begin
			P=0;
			L=1;
		 end
	 s3:begin
			P=0;
			L=1;
		 end
	endcase
end
endmodule

Thanks&Regards

 

[ahmad1954]

in verilog you should always determine size of your parameters otherwise verilog consider it 32 bit and most of time a lot of warning happens like this. in this case you should put s0=2'b00, s1=2'b01, s2=2'b10, s3=2'b11

 

[arishsu]

Thanks a lot. That worked.