Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

state diagram for benchmark circuit

Status
Not open for further replies.
M

MEENAKUMARI

Newbie level 4
Joined
May 7, 2012
Messages
6
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,314
Sir,

For my project i need the state diagram for sequential benchmark circuit s27.Please help me.
 

What is "sequential benchmark circuit s27"?
Can you show the circuit, or give a link?
 

S27 is available in ISCAS89 Sequential Benchmark Circuits
 

OK, I wasted my time googling "ISCAS89 Sequential Benchmark Circuits", but all I found was this web page, with a link to a .bench file, whatever that is. Sorry, can't help.
 

I cannot read the codes for such a diagram in Verilog. If you can take out the connection of the circuits, I can answer you!!
For further contact, you could mail me: <cleveryj@126.com> or <yujiang2016@163.com>!!
 
Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top