OK her is several my question,
My first design , very simple RS Flip Flop with Q output and AND gate with x,y input.
VHDL code below.
Question.
1. How connect Q output RS FF with y input AND gate? (internal connect inside FPGA)
2. How connect on x input of AND gate clock from external differencial LVPRCL driver?
3. Is inside ISE any tool which say me how maximal frequency is applicable for this design inside Spartan 3A?
Thansk you
-----------------------------------------------
- RS Flip Flop -
-----------------------------------------------
entity RS is
port (reset, set: in std_logic;
q : out std_logic);
end RS;
architecture rtl of RS is
begin
process (reset, set) begin
if (reset = '0') then
q <= '0';
elsif (set = '0') then
q <= '1';
end if;
end process;
end rtl;
-----------------------------------------------
- AND GATE -
-----------------------------------------------
entity AND_ent is
port( x: in std_logic;
y: in std_logic;
F: out std_logic
);
end AND_ent;
architecture behav of AND_ent is
begin
F <= x and y;
end behav;