Start/Stop Counter Using Finite State Machine (Verilog)

[hsnhsyn1]

Hi, I'm trying to design a counter using finite state machine, with a start and a stop input. as output, I need the count value for calculating the time between start and stop signals.

I calculated my max. count value as 90000, 17 bits (90 ms, with 1 MHz clock frequency). By the way I'm not sure if I must use a max value or not.

I have read and understood some counter examples as finite state machine, but they were all small values of count, for example modulo 8. So I can't figure out how to do it.

Thanks for any help.

Edit: I made a state diagram with two states; in stats S0, machine waits for the start input to go high. when start signal is high, it moves to state S1 and Enables the counter to count until the stop signal comes. When the stop signal comes it moves back to the state S0.(But I don't know if it is okay or not)

 

[harishrv]

Hi ,

Can you send me the code . I think, your edit field is saying , u are doing the correct thing.

 

[xtcx]

Please post your code....

 

[hsnhsyn1]

This is my code for the state machine. I used the output signal CountEnable to enable my counter. I also simulated this state machine with the counter i think it counts fine, but i have some "ripples" between some values while counting which seems not effecting the count value and i don't know why it's occuring.

module FSM_TRY
(
	input 	Clock,
	input 	Reset,
	input 	Start_timer,
	input	Stop_timer,
	
	output	reg CountEnable,
	output	reg ResetCount
);

parameter 	IDLE 	= 2'b00;
parameter	COUNT	= 2'b01;
parameter	DONE	= 2'b10;

reg [1:0] state, next;

always@(posedge Clock)
	if(Reset)	state <= IDLE;
	else		state <= next;

always@(state or Start_timer or Stop_timer)
begin
	next = 'bx;
	case(state)
		IDLE: 	if(Start_timer)	next = COUNT;
				else	next = IDLE;
		
		COUNT:	if(Stop_timer)	next = DONE;
				else	next = COUNT;
		
		DONE:			next = IDLE;
	endcase
end

always@(posedge Clock)
	if(Reset)		CountEnable <= 1'b0;
	else
	begin
		ResetCount <= 1'b0;
		CountEnable <= 1'b0;
		case(next)
			IDLE	: ResetCount <= 1'b1;
			COUNT 	: CountEnable <= 1'b1;
			DONE  	: CountEnable <= 1'b0;
		endcase
	end
endmodule

This is the "ripple" i mentioned.


and this is the overall simulation result


if you have some suggestions to improve/correct the code i would be grateful.

Edit: I also have this warning during simulation:

Warning: Can't display state machine states -- register holding state machine bit "|FSM_Counter|FSM_TRY:CounterFSM|state.COUNT" was synthesized away

I checked it on Quartus help but couldn't find anything useful.

 

[FvM]

To understand the nature of what you call "ripple" please expand the counter value in simulation and watch the individual bits. This is a QSIM timing simulation, it's showing a realistic output signal of the respective device.

What you see is so called "delay skew" and just normal operation. By nature of synchronous logic, the counter value has to be stable before the next clock edge.

A possible problem that's not handled in your state machine is with asynchronous input signals. Your state machine will only work correctly, if the start/stop signals are synchronous to the design clock, generated inside the FPGA rather than external signals.

 

[hsnhsyn1]

I don't know whether I can do it or not, but I was thinking to generate the start/stop signal after the analog digital conversion. I'm using two channel ADC for two analog sensors. Sensors give maximum output while at rest, and when an object comes, the output voltage decreases. So I thought that I can generate the start signal when the first sensor differs from the max. value and generate the stop signal when the second sensor differ from the max. value.
But the method may be wrong because I haven't asked my teacher about this.

 

[FvM]

The question is how the start stop signals are generated. I just wanted to mention a possible problem, beyond your actual question.