module FSM_TRY
(
input Clock,
input Reset,
input Start_timer,
input Stop_timer,
output reg CountEnable,
output reg ResetCount
);
parameter IDLE = 2'b00;
parameter COUNT = 2'b01;
parameter DONE = 2'b10;
reg [1:0] state, next;
always@(posedge Clock)
if(Reset) state <= IDLE;
else state <= next;
always@(state or Start_timer or Stop_timer)
begin
next = 'bx;
case(state)
IDLE: if(Start_timer) next = COUNT;
else next = IDLE;
COUNT: if(Stop_timer) next = DONE;
else next = COUNT;
DONE: next = IDLE;
endcase
end
always@(posedge Clock)
if(Reset) CountEnable <= 1'b0;
else
begin
ResetCount <= 1'b0;
CountEnable <= 1'b0;
case(next)
IDLE : ResetCount <= 1'b1;
COUNT : CountEnable <= 1'b1;
DONE : CountEnable <= 1'b0;
endcase
end
endmodule