Dear Googler
You have said that you have standard cell.
Do you have Liberty file (.lib) prepared for synthesis tools and ... or you have spice netlist of all cells such NAND ,NOR, INV , .... ?
If you have The spice netlists, The transistor sizes and structures of each cells are clear.
But if you have a .lib File, The file has not the information about circuitry of the cells.
In the Liberty file, There is plenty of tables of the data which say the delay, power of the cells in various conditions (inputs, ...).
Then after all, which of them do you have?
Standard cells will have same heights because if it differs we cant place it in the row of power and ground line... in the sense cells will be placed between power and ground stripes.. Look at the cell placement in the placement step of pnr u can see there may be double triple height standard cells(Its not same always)..... The thing is width may have any value but the height should be double triple etc..,
also for question 3 i cant predict what you are coming to convey...