standard cell placement using Cadence SoC Encounter

[aria62]

Dear friends,

I'm trying to create layout using SoC Encounter. these are the steps i follow:
1.loading my vhdl code into synopsys design vision
2.compiling the design using "lsi10k" library as link, target and symbol library.
3.creating verilog gate level netlist and sdc file.
4.loading verilog gate level netlist, timing libraries and sdc file and lef files into SoC Encounter.These are my lef TSMC0.18 files from ARTISAN:
tsmc18_6lm_cic.lef
tpz973g_5lm_cic.lef
tsmc18_6lm_antenna_cic.lef
antenna_6_cic.lef

5.floorplanning
6.powerplanning
7.standard cell placement

I can easily do standard cell placement for a single 2 to 1 multiplexer using these steps. But when I perform the same process for a decoder, many warnings arises and standard cell placement fails.
some of these warnings are as follows:

**WARN: (SOCDC-1151): No instances found in the design. Check if your design have instances other than filler cells.

**WARN: (SOCVL-346): Module NR2 is not defined in LEF files. It will be treated as an empty module.
Module ND2 not defined. Created automatically.
**WARN: (SOCVL-346): Module ND2 is not defined in LEF files. It will be treated as an empty module.
Module IVP not defined. Created automatically.
**WARN: (SOCVL-346): Module IVP is not defined in LEF files. It will be treated as an empty module.
Module OR2P not defined. Created automatically.
**WARN: (SOCVL-346): Module OR2P is not defined in LEF files. It will be treated as an empty module.

I attached the verilog gate level netlist and encounter log file.Can anyone help me and give a clue to solve the problem?
Thanks in advance.

 

[iwpia50s]

Looks tome like your LEF library doesn't match your timing library or your Verilog netlist

 

[aria62]

Looks tome like your LEF library doesn't match your timing library or your Verilog netlist

Does anybody know Synopsys Design Vision library and SoC Encounter lef files which match together?