[SOLVED] Stacked NMOS or HV devices for high voltage driver design

[rissenaj]

Hi all,

I have a design that need to have an output voltage swing of 20V and the level shifter and the driver need to be fabricated on the same chip. I have come across a lot of high voltage processes which allows the integration of low and high voltage devices on the same chip.

I read a paper on high voltage series MOSFET output driver which achieves the driver functionality using stacked NMOS or stacked PMOS or stacked NMOS and PMOS in push-pull configuration. What's the main difference in using HV devices for output drive vs stacked LV devices? My main objective is area and power. Thanks in advance.

Regards
rissenaj

 

[dick_freebird]

My experience is that a LDMOS device standing off 20V,
has better on-resistance than a standard FET stack of
equivalent capability. This is, perhaps, because the
LDMOS drift region is modulated to higher conductivity
when "on".

If your LV devices don't have a well that is independent
and can be biased to (say) 17V from substrate, you
are still in a bind. And a flying well, times 5, is a lot of
capacitance to charge and discharge, to leak and so
on.

Using 5 devices when one will do is seldom a winner,
except perhaps for avoiding the expense of extra mask
layers and process steps.

The LDMOS of which I spoke used a 1um channel and
a 1um drift region, vs a stack of 6 0.5um FETs. So an
area win, also, for power density.

But that power density, when the FET is run outside
a hard switching, on or off, application, will blow the
device up. You can't achieve infinite power density
in either case. Low power level shifter, OK. High
delivered power, efficiently, OK. High dissipated power,
not OK.