Compare to the common source power amplifier, the stacking K FETs power amplifier's current is increased by K? Is that right? (Assuming the loadline inpedance is fixed as RL)
I don't think the current is increased by the exact number of stacked FETs, but might be increased somehow to compensate for decreased efficiency (loss rate per stacked stage). The stacked stage needs an optimization to get required output power and efficiency (and linearity).
Meanwhile, each stacked transistor must provide a resistive load Ropt, in a away that the series connection of all stacked transistors is equal to the load RL need to be driven.