Let me be very specific then, Let's say i have a FPGA(controller)having 50ms of bootup time. generating PWM of 200KHz regulating a Buck plant.Now, the idea is, without using any Hold up ckt for the FPGA Power supply, if the Power supply for the FPGA gets interrupted due to 'change' in Power Supply source, happening only once the board is powered up How could i maintain the PWM for the 50ms, as if i use PLL, it would be able to lock the frequency not the pulse width?
@KlausST : It's the Capacitor size which for 50ms duration and 5 Amps of Current points to 50mF Cap. My priority is to have small form factor for my application using small SMD components. So, I am trying to think on the alternate lines.