By parasitics I mean the resistance and capacitance values (R&C) of the nets which play a major role in determining the timing performance of a circuit. A SPEF includes this as well the flop delays and gate delays. An SDF includes only the flop delays and gate delays and is therefore inaccurate.
SPEF file has R and C values which the STA tool uses to calculate and arrive at cell and net delays and compute the crosstalk information.
SDF has annotated delays and cells are annotated with the delays. STA tool just has to annotate these delays and there is no computation involved.
Usually SDF is written out from STA tools as an input for simulation, and SPEF is read in to STA tool so that it can compute the delays.
By parasitics I mean the resistance and capacitance values (R&C) of the nets which play a major role in determining the timing performance of a circuit. A SPEF includes this as well the flop delays and gate delays. An SDF includes only the flop delays and gate delays and is therefore inaccurate.
From your point the delay is calculated from R & C parasatics in SPEF file .
But in SDF file from ICC also contain interconnect and gate delay (After P & R).
Then why seperation between SPEF and SDF? confusing!!!
SPEF file has R and C values which the STA tool uses to calculate and arrive at cell and net delays and compute the crosstalk information.
SDF has annotated delays and cells are annotated with the delays. STA tool just has to annotate these delays and there is no computation involved.
Usually SDF is written out from STA tools as an input for simulation, and SPEF is read in to STA tool so that it can compute the delays.
This answer explains the most. Both SDF and SPEF are generated by PnR tool, and imported to PT for timing analysis. Because SPEF contains RC info, it can be used for signal integrity check in PT SI also.