I believe skew is different than you described here .. from wikipedia -
In a synchronous circuit, clock skew (TSkew) is the difference in the arrival time between two sequentially-adjacent registers. Given two sequentially-adjacent registers Ri and Rj with clock arrival times at register clock pins as TCi and TCj respectively, then clock skew can be defined as: TSkew i, j = TCi - TCj
so it's not mean max latency and min latency ... there is difference between latency and skew , and both are different term ..
but relationship is close between latency and skew ..