good questions
1) Synthesis just transform RTL to gate level netlist. It does not check timing. STA checks timing and tells you the the slowest path in the design which determines the maximum frequency of the design. Note for STA you need synthesized design and synthesis library with timing information. From this, STA tool will determine the slowest path in the design.
2) You need to do post STA simulation to see if STA results are indeed correct. Since STA tool needs constraints which are given to STA tool by humans, it may contain errors. That is why post synthesis simulation is necessary to gain confidence.