bravoegg
Member level 2
I'm trying to use Xilinx Srio Ipcore and could generate the example design( generated automatically by Vivado) which could be simulated properly. However it only simulates properly when I change nothing in the ipcore GUI.
The default transfer frequency is 5Gbaud. I will need to use 3.125Gbaud .
But after I set the transfer frequency to 3.125Gbaud and leave other items as it is, and again generate the example design. Later in the simulation the link_initialized and port_initialized signals are never valid.
I wonder why it failed? Please help....thanks in advance.
The default transfer frequency is 5Gbaud. I will need to use 3.125Gbaud .
But after I set the transfer frequency to 3.125Gbaud and leave other items as it is, and again generate the example design. Later in the simulation the link_initialized and port_initialized signals are never valid.
I wonder why it failed? Please help....thanks in advance.