Thank you for answering,
by definition, you cannot.
I may have poorly defined my intentions. By simultaneous i meant two blocks accessing a shared resource, in this case - SRAM chip.
VGA controller have a precise timing it should follow on reading.
Writing (or another reader) is not time-critical, and can wait a little, but should be able to proceed without interrupting the drawing or delaying for too long.
I would have expected this kind of problem being solved long ago, since there are CPUs accessing graphic memory in linear buffer, or multiple CPUs accessing shared memory, or various memory-mapped I/O things, etc.
That is the kind of simultaneous access i need to get.
As for locking\mutex\arbiter - i get the algorithm, but i have no idea how to implement it.
For example:
The simple writing code:
(*= AT symbol, the forum complains if i use it)
Code:
wire [2:0] sram_select=1+SW[0];
reg [15:0] sram_wr_data;
wire [15:0] sram_write_data;
reg [17:0] wr_sram_addr;
assign sram_write_data=sram_wr_data;
always *(posedge CLOCK_50)
begin
if(wr_sram_addr>=153600)wr_sram_addr<=0;
else wr_sram_addr<=wr_sram_addr+1;
sram_wr_data<=wr_sram_addr
end
SRAM access, whether 1 or 2 is used is selected by sram_select:
Code:
Multi_Sram the_sram(
//Side 1
.oAS1_DATA(mSRAM_VGA_DATA),
.iAS1_ADDR(sram_vga_addr),
.iAS1_WE_N(1'b1),
.iAS1_OE_N(1'b0),
//Side 2
.iAS2_DATA(sram_write_data),
.iAS2_ADDR(wr_sram_addr[17:0]),
.iAS2_WE_N(1'b0),
.iAS2_OE_N(1'b1),
//Control Signals
.iSelect(sram_select),
//SRAM
.SRAM_DQ(SRAM_DQ),
.SRAM_ADDR(SRAM_ADDR),
.SRAM_UB_N(SRAM_UB_N),
.SRAM_LB_N(SRAM_LB_N),
.SRAM_WE_N(SRAM_WE_N),
.SRAM_CE_N(SRAM_CE_N),
.SRAM_OE_N(SRAM_OE_N)
);
The VGA have an output of sram_vga_addr, and it's own clock to set it by.
mSRAM_VGA_DATA is decoded to the VGA output.
Arbiter, based on code in asic-world tutorials, takes (clk,req1,req0,gnt1,gnt0).
So, the code is supposed to set the request, detect the grant, act, unset the request, wait for the next clock.
Same goes for VGA code.
But how to make it do that?
How to link it all up?
I don't understand a few things here - how long should it take for the VGA output and read from memory to take effect?
How long does it take to write to memory?
How and at what moment could i unset request for VGA read?
Is it conceivable to run the writer at twice the clock of VGA, and each second half to write to memory?
How many reads/writes can i hope to get before VGA is disrupted regardless?
All in all, how are such thing done properly?
ping-pong buffers are another concept.
Not really an option, as there is just enough memory for one frame.
In any case, i want to figure out how to access a shared resource.