*source
vdd vdd 0 dc 2
CBL BL 0 1pf
CBLB BLB 0 1pf
*initial conditions stored for read operation
.ic v(Q)=1
.ic v(QR)=0
.ic v(bl)=1
.ic v(blb)=1
*access control
vwl wl 0 pulse(0 2 4m 100u 100u 5m 6m)
*transistors used for latching
sw7 QR 0 Q 0 smod2
sw8 QR vdd Q vdd smod1
sw9 Q 0 QR 0 smod2
sw10 Q vdd QR vdd smod1
*transistors used for data access
sw11 bl Q wl 0 smod2
sw12 blb QR wl 0 smod2
.tran 10m 100m uic
.probe
.MODEL Smod1 VSWITCH(Ron=1000 Roff=1 Von=1V Voff=0.5V)
.MODEL Smod2 VSWITCH(Ron=1 Roff=1000 Von=1V Voff=0.5V)
.end