Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

SRAM problem Spartan 3

Status
Not open for further replies.

moottii

Full Member level 2
Full Member level 2
Joined
Feb 22, 2012
Messages
120
Helped
13
Reputation
26
Reaction score
13
Trophy points
1,298
Visit site
Activity points
1,962
Hello friends,
Could you please introduce some sources of operation of SRAM asynchronous or please explain how does it work?I searched, but I couldn't find useful tutorial.
For example: for writing operation what should be done?
I wanna implement BIST(built-in self-test) for SRAM on Spartan 3 FPGA.(SRAM model: K6R100V1C)
 

No, I don't have.
The only thing that I have is the pin number which indicates : [A16:A0] , [I/O8:I/O1], /CS, /OE, /WE.
have you experienced working with SRAM? if yes, what should be done for writing/reading operations for a typical SRAM?
 

Type "asynchronous SRAM write" into Google and the first hit is a PDF tutorial from Cypress on SRAMS with sn explanation of how they work complete with timing diagrams. You can find it here.
**broken link removed**

r.b.
 
Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top