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SRAM Power dissipation

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020170

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Following Table shows that SRAM power dissipation in writing and Reading operation.

( It's from "A Low Power SRAM USing Hierarchical Bit Line And Local Sense Amplifiers, IEEE, 2005" )

The SRAM consumed 28mW at Write operation.

Question : What is "Write operation" refered in this paper?

Is it that Power dissipation needed to write only One Cell?

or Total Power dissipation "on Writing operation" ?

thanks
 

analog_prodigy

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I think, it's the power dissipation for writing operation at once.
 

    020170

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A.Anand Srinivasan

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i think it is for a writing a particular number of cells or writing the whole array of cells at once.... because the only the power dissipation would be this high for CMOS technology....
 

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Dynamic Power Dissipation Or Static Power Dissipation?

In my thought, Dynamic Dissipation is ture.
 

A.Anand Srinivasan

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i think it is dynamic for writing operation and static for read operation....
 

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A.Anand Srinivasan said:
i think it is dynamic for writing operation and static for read operation....
I don't Understand why consumed static power dissipation in reading operation.

is it right that consume dynamic power dissipation in reading operation, too ?

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A.Anand Srinivasan

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while reading the MOS doesnt change state...

dynamic power is when a memory element switches... for writing they would have calculated worst case and hence i assume they would have switched....
 

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