SRAM based FPGA for fault tolerance

[rahulmlokurte]

I want to know where exactly SRAM cells are present in FPGA?

 

[shaiko]

FPGAs made by Altera and Xilinx have the main FABRIC constructed of SRAM cells. Combinatorical logic is implemented using these cells.
Actel on the other hand uses FLASH technology instead of SRAM - non volatile and less power hungry. However, the manufacturing process of SRAM is usually more advanced (in the nm range) which yeilds higher logic density and enables greater speeds.

 

[rahulmlokurte]

Thank You Shaiko,but I need information specifically about xilinx virtex-5 FPGA.Where do we find SRAM cells in that?

 

[shaiko]

Again,

It doesn't matter whether it's Spartan 3/ Spartan 6/ Virtex 6/ Virtex 7 or the Virtex 5 your interested in.
SRAM isn't a "feature" of the device or something that the device "has to offer" like an mp3 player in an automobile. SRAM cells make the actual FPGA fabric!

Please read this:
FPGA Architectures Overview

 

[rahulmlokurte]

Thank you shaiko. website you mentioned was helpful!!!

 

[shaiko]

Sure - glad to help.

"SRAM based FPGA for fault tolerance" - what fault tolerance are you looking for?
Is there a particular reason you decided to go with the Virtex 5 ?

 

[rahulmlokurte]

In my project,i am assuming that LUt's are stuck at faults.Using BIST technique,i have detected that there are faults.Now i need to diagnose and correct such type of faults. Due to availabilty of virtex-5 in college,i am going with that. Can you please suggest me some books or links which would help.?

 

[shaiko]

Sure, I can reccomand some good books. Please let me know what is your knowledge level.
Are you familiar with the fundamentals of digital circuitly (flip flops, muxes, decoders, logic gates, ram...)?
Do you have any experience with VHDL or Verilog?

 

[rahulmlokurte]

Yes, I am familiar with digital logic. I know both VHDL and Verilog. We had those subject in our academic.Please suggest me about fault diagnosis and fault tolerance.

 

[shaiko]

Before reffering to literature...
If you're 100% sure that the errors aren't the result of a faulty design - I suggest you try the following:

1. Read the synthesis report and look for timing violations
2. Try to decrease the clock speed to see if it helps.
3. Using the ISE tool - optimize synthesis for speed.
4. Integrate an error correction code into your design (Hamming is the simplest).
5. Use a CRC generator to check for errors.

If your FPGA interconnects to external components and the design is running at high speeds it may be a PCB signal integrity issue. Make sure that the I/Os buffer settings are set correctly.

Now, the literature:

**broken link removed** (an interesting article).
"A VHDL Primer" - Bhasker (good starting point for leaning VHDL).
"The Designer's Guide to VHDL" (a more advanced and very good book).

But first - MAKE SURE THAT THE DESIGN IS 100% CORRECT!