[SOLVED] squaring a fixed point number

[nakshathra]

Hi,

I have a std_logic_vector(16 downto 0) which stores a fixed point number in which, the bits (16 downto 8) store the integer part of the fixed point number and (7 downto 0) store the fractional part of the fixed point number.
Now, I need to square the number to obtain the result in another std_logic_vector(16 downto 0) with the same convention.

e.g.
entity square is
port( a: in std_logic_vector(16 downto 0)
b: out std_logic_vector(16 downto 0));
end square;

if input is 1.45, ie a<= "00000001 01110011"
then the output should be 2.1025, ie b should result it "00000010 00011010"

I know the problem simplifies using sfixed type, but my requirement is in std_logic.

I tried coding, but it din't work out..
I would be pleased if someone helps me out with an idea of solving it.

Thanks in advance!

 

[TrickyDicky]

Whats wrong with the sfixed type? it is an array of std_logic just like std_logic_vector. or why not the signed type from numeric_std? you can still output a std_logic_vector via type casts

either way, after squaring, you need to remove the 8 MSBs and 8 LSBs (because 16.8 x 16.8 = 32.16). you probably need to consider saturation and rounding to prevent rollover.

if you absolutly have to use std_logic_vector, there is the non-standard library std_logic_signed. It has a * function.

 

[nakshathra]

I have done over half my code using std_logic_vector and m stuck at this point where squaring has to be done. How can I use signed type?

The removal of 8 MSBs and 8 LSBs is not a problem coz i don't work on large numbers and require only 8 bit precision. Well, 16 and 32 can be accommodated in 8 bits.

 

[TrickyDicky]

using signed type is going to be the same as using std_logic_vector. If you want to stick to non-standard VHDL, for the squaring you just do this:

signal temp : std_logic_vector(32 downto 0);

temp <= a * a;
b <= temp(24 downto 8);

using signed type is almost identical:

signal temp : signed(32 downto 0);

temp <= signed(a) * signed(a);
b <= std_logic_vector( temp(24 downto 8) );

This is why you need to be using the signed type at the port level....

Are you sure your input is never going to be more than +8 or less than -8? if this is the case, why bother with a 16 bit input? why not 4 integer bits? If the input can be greater than 8, you're going to have overflow problems. You also need to consider rounding, otherwise you floor the output.

 

[nakshathra]

i hope you got that m using a fixed point number notation in std_logic_vector.
the * operator really doesn't work, because a number 1.5 is stored as "00000001 10000000" which is recognized as 384. Hence the * operation results the square of 384 but not 1.5.
It's quite complicated!
May be I should restart with sfixed.

the input is never going to be negative and is always a fixed point number between 0 and 255.

 

[TrickyDicky]

That doesnt matter, I extracted the correct bits to leave it as a fixed point.

1.5 squared = 2.25

00000001 10000000 ^ 2 = 00000000 00000010 01000000 00000000

Hence remove the 8 MSBs and 8 LSBs and you get the correct number as a fixed point thats only 16 bits.

- - - Updated - - -

Fixed point is just integer arithmatic. The integer and fractional separation is just a figment of your imagination.

You just have to manage the separation of integer and fraction inside your integer.

a 16 bit number squared results in a 32 bit result. A 8.8 number (8 integer, 8 fraction) squared results in 16 integer and 16 fraction.

so a.b * c.d = (a+c).(b+d)
then you just trim the bits appropriatly if you want fewer bits.

 

[nakshathra]

Gotcha!!
Thanks a ton! :smile: