Square of 2-bit input in Verilog

[LavezLas]

Hi guys,

First of all, I'm glad that I'm a part of this forum by this day.

Here is my question; teacher wants us to design a circuit that calculates the square of its 2-bit integer input A=(a1,a0) and
produces the output B. He wants verilog codes with 3 types;

1)Write the Verilog code by using “if” or “case” statements
2)Write the Verilog code of the logic diagrams by using “Dataflow modeling” method
3)Write the Verilog code of the logic diagrams by using “Structural modeling” method

I think it will be very easy for you, a quick reply would be very nice

 

[mrflibble]

I'm not even going to try a new one. Copy/paste an old reply. I am sure you can appreciate the amount of work I put into this.

<copy>
Satan helps those that do their own homework.

Same for Jesus, Buddha and Thor. It's mostly a placeholder for "you" really. So what fine attempts have you done so far for this assignment and where are you stuck?
</paste>

Hope the reply was fast enough for you, and helps clarify matters on this whole "homework" concept.

 

[LavezLas]

I did something of course, here is the code I tried to write;

module SQUARE(a1,a0,b3,b2,b1,b0);
input a1,a0;
output b3,b2,b1,b0;
reg b3,b2,b1,b0;

always @ (a1 or a0)
begin
if ((a1==0) && (a0==0)) {b3,b2,b1,b0}=4'b0000;
else if ((a1==0) && (a0==1)) {b3,b2,b1,b0}=4'b0001;
else if ((a1==1) && (a0==0)) {b3,b2,b1,b0}=4'b0100;
else if ((a1==0) && (a0==0)) {b3,b2,b1,b0}=4'b1001;

end
endmodule

 

[TrickyDicky]

where is the source clock? or is he expecting a combinatorial design?

 

[LavezLas]

I didn't understand your question actually, but here is a picture of what he wants;

 

[mrflibble]

1) what TrickyDicky said.

2) I would suggest using bit vectors instead of all the seperate bits (a1, a0)

3) use this style of port notation:

module SQUARE(
    input  [1:0] a,
    output [3:0] b
);

And 4) ... DONT do if .. else if like that, it will synthesize a priority encoders that you did not intend... Use a case statement, making sure to include all possible states, and handle the "default" case as well.

5) See 1. Right now your output is combinational. It is good practice to register the output of your modules.

 

[LavezLas]

module SQUARE(B,A,S);
input [1:0]A;
input [1:0]S;
output [3:0]B;
reg [3:0]B;

always @ (A or S)
case (S)
2'b00 : B = A*A;
2'b01 : B = A*A;
2'b10 : B = A*A;
2'b11 : B = A*A;
default : B = 4'zzzz;
endcase
endmodule

So I tried with what you said, but still a error occurs. "SQUARE.v" line 33 unexpected token: '4'
What is wrong ?


SOLVED: I forgot the "b" right to the '. :smile:

- - - Updated - - -

Now I think I did it, here is the last what I wrote;

module SQUARE(B,A);
input [1:0]A;
output [3:0]B;
reg [3:0]B;

always @ (A)
case (A)
2'b00 : B = A*A;
2'b01 : B = A*A;
2'b10 : B = A*A;
2'b11 : B = A*A;
default : B = 4'bzzzz;
endcase
endmodule

 

[mrflibble]

*grin* that case statement!! XD Not entirely what I meant though... Also, B=4'zzzz ... while this does mean something and results in some circuitry ... what do you think you are going to get there? Because I doubt it will be what you intend, unless you have a very specific purpose.

Also, what is S? you magically conjured up that one.

Aaaand, this is still combinational.

Edit: Heh, your edit is without S. Well, that makes a bit more sense.

- - - Updated - - -

output [3:0]B;
reg [3:0]B;

Better do this:

output reg [3:0]B;

In fact better do what I told you before! But now with your added feature of wanting B to be a register (not a bad idea).

module SQUARE(
    input      [1:0] a,
    output reg [3:0] b
);

Also, note the ABSENSE of any "input a" "reg whatever b" after this style of module declaration. This takes care of it.

And now that you have a register, better put a clock in it. And read that digital design book that you should have been reading.

 

[LavezLas]

Thanks for all the contribution mate, cheers