The problem is Why the distortion / Spiking's decreases as current increases?
Can we over come this effect when there is no load?
and why is this happening?
Please consider forum rules about uploaded images:
Avoid using bmp image format, it occupies a huge size compared to the formats described above and can’t be shown directly in a browser which is an additional inconvenience.
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If you look sharp, you'll realize that the load resistance doesn't actually reduce the peak-to-peak ringing magnitude. It only removes the overshoot by adding a low-pass response caused by the transformer leakage inductance. Hence the ringing is hidden in rising edge.
It would be interesting to look at the primary waveform, e.g. bridge center to DC-. Most likely, the ringing already present it the bridge output, caused by parasitic circuit inductance.
Ah sorry about the .bmp
next time i will send it as jpg. Also I've the Primary sides figure below
it looks the same as in the secondary side (also that figure was taken when there was no current)
Isn't it possible to reduce the effects of parasitic capacities?
or maybe can we reduce these effects by choose a lower Cgs, Cgd, Cds values of mosfet?
the whole ckt would be useful to answer your questions, but in short, too open a layout with no nearby bus caps causes the sort of effects you are seeing ...