I expect your ringing is mostly external to the
IC. Most likely the SRF of decoupling caps in the
context of their local layout, but also any distance
between probe ground point and signal (a loop
to pick up edge EMI).
I'd expect if you put a few nH in the circuit between
decoupling cap and IC, decoupling cap and ground
and some between IC ground and ground plane
(as realistic as you can manage) your simulated
ring-note would shift down toward bench readings.
So too, any info you can find on capacitor(s) ESL
and ESR, if you care about this stuff then each cap
wants a valid subcircuit model plus some top
level expression of its access R, L, C.